1. Field of the Invention
The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly, to a semiconductor having an interconnect structure with improved reliability and a method of manufacturing the same.
2. Description of the Related Art
As transistors have become smaller and smaller, logic devices having higher speeds and higher integration have been made. As the integration of transistors increases, the dimension of interconnects has shrunk. However, as interconnects have become smaller, a delay problem caused by the interconnects has become more acute, and thus, the delay caused by the interconnects has become an obstacle to high-speed logic devices.
Under such a situation, interconnects using copper, which has lower resistance and higher electromigration (EM) tolerance than an aluminum alloy, which was conventionally and generally used as a material of interconnects of large scale integrated (LSI) semiconductor devices, have been actively developed. However, there are problems with using copper: it is not easy to etch and is oxidized during a process for forming the interconnects. Accordingly, a damascene process is used to form a copper interconnect. The damascene process is used to form trenches, which are formed between upper layer interconnects for respectively isolating the upper layer interconnects formed on insulating layers, and vias for connecting the upper layer interconnects to lower layer interconnects or a substrate. The trenches and the vias are filled with copper, and the trenches and the vias are planarized by a chemical mechanical polishing (CMP) process.
A dual damascene process is often advantageously employed because it is used to form a bit line or a word line as well as to form metal interconnects, and it enables vias for connecting the lower layer interconnects to the lower layer interconnects to be simultaneously formed in a multi-layered metal wiring structure. In addition, a step difference generated by the metal interconnects can also be removed through the dual damascene process. Consequently, the dual damascene process facilitates subsequent processes.
Copper (Cu) used in the metal interconnects of a semiconductor device has several characteristics, including a high diffusion rate into an adjacent insulating layer or substrate. The copper diffused into an active area other than the metal interconnects may operate as impurities. Therefore, it is necessary to form a diffusion barrier layer in order to limit diffusion of copper into the insulating layer or substrate.
In a semiconductor device to which a conventional copper interconnect is applied, failure of a semiconductor device may often occur due to thermal stress in a subsequent thermal process. In particular, when a via is formed between an upper interconnect and a lower interconnect and the upper interconnect and/or the lower interconnect have a large line width, concentration of thermal stress may be created between the upper interconnect and the via or between the via and the lower interconnect, forming a so-called stress induced void (SIV), or vacancy at an upper or lower portion of the via, thereby ultimately resulting in electric shortage. The electric shortage may occur, especially when an insulating layer for covering the interconnects has a small Young's modulus and a large heat expansion coefficient. In such a case, the adhesion property between a via and each of interconnects is deteriorated at the surface where the via and the interconnect contact; thus, the sheet resistance of the interconnect increases, resulting in a deterioration in the reliability of the interconnect.